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Cypress Semiconductor /psoc63 /BLE /RCB /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_CLK_EDGE)TX_CLK_EDGE 0 (RX_CLK_EDGE)RX_CLK_EDGE 0 (RX_CLK_SRC)RX_CLK_SRC 0 (SCLK_CONTINUOUS)SCLK_CONTINUOUS 0 (SSEL_POLARITY)SSEL_POLARITY 0LEAD 0LAG0 (DIV_ENABLED)DIV_ENABLED 0DIV0ADDR_WIDTH 0 (DATA_WIDTH)DATA_WIDTH 0 (ENABLED)ENABLED

Description

RCB control register.

Fields

TX_CLK_EDGE

N/A
RX_CLK_EDGE

N/A
RX_CLK_SRC

N/A
SCLK_CONTINUOUS

N/A
SSEL_POLARITY

N/A
LEAD

N/A
LAG

N/A
DIV_ENABLED

N/A
DIV

N/A
ADDR_WIDTH

N/A
DATA_WIDTH

N/A
ENABLED

N/A

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data